1. Field of the Invention
The field of the invention may include signal alignment among active electrical devices, circuits, and systems. More particularly, the invention may include employing a transmitted data signal as a clock signal to align this clock signal in a receive device with the incoming data signal.
2. Background Information
A computer may be thought of as a machine that may be programmed to manipulate symbols. Computers may perform complex and repetitive procedures quickly, precisely and reliably and may quickly store and retrieve large amounts of data. The physical devices (or components) from which a computer may be constructed (electronic circuit devices and input/output devices) are known as xe2x80x9chardwarexe2x80x9d. Most computers have four types of hardware devices: central processing unit (CPU), input, output, and memory. The CPU executes programs (xe2x80x9csoftwarexe2x80x9d) that tell the computer what to do. Input and output (I/O) devices allow the computer to communicate internally among devices and externally with a computer user or other computers. Memory devices may be used to hold intermediate results or to hold programs, application instructions, and database field information.
The last century has seen increasingly complicated networks of machines and systemsxe2x80x94satellites, Internet nodes, electrical grids, landline and cell-based phone communications. For those networks to carry out coordinated actions, each needs to agree on the time as they communicate with one another. In order to share information, a computer or a network of computers needs to know when to speak, when to respond, and at what rate to do so. In this sense, the amount of information a computer or a network may distribute is directly related to how fast that information may be transmitted and how accurately time may be synchronized within the computer or across a network.
Intermediate results, programs, application instructions, and field information from database records may be distributed within a computer system as data signals in the form of ones and zeros. To send two data signals along parallel buses to a first and second data port in receive device, for example, a transmit timing signal (or xe2x80x9cclockxe2x80x9d) conventionally is sent to a clock recovery device associated with the receive device in advance of the data signals, such as at initialization. This transmit timing signal may be transmitted in the form of a wave having a series of voltage changes that are identified as edges.
On receiving the timing signal, the receive device splits the transmit timing signal into a first timing signal and a second timing signal. These two timing signals are then each routed through a clock buffer, one for each data signal, to the first and second data ports. Each clock buffer uniquely shifts the edges of its own timing signal to account for timing skews that affect the travel speed of its associated timing signal. Timing skews accounted for by a clock buffer may result from variations in the materials used to manufacture one computer to the next, manufacturing tolerance and techniques, and variations in voltages and temperatures as the computer operates over time.
The conventional goal in the above example may be to align the edge of the first timing signal to the center of the first data packet and align an edge of the second timing signal to the center of the second data packet. The problem with this approach may be that the first timing signal edge and the second timing signal edge originate from the same source, namely an edge of the transmit timing signal. Since the receive device splits the transmit timing signal into a first timing signal and a second timing signal, the above approach may be the equivalent of trying to align the one waveform edge of the transmit timing signal to two different data packet centers. Even if this one edge was aligned with the center of the first data packet, timing skews introduced into the second data packet by the transmit device and by the bus over which that data signal travels will most likely result in an undesirable misalignment between the waveform edge and the center of the second data packet.